For a PLL circuit, a voltage controlled oscillation circuit of which an oscillation frequency is controlled according to an input voltage is used (see, for example, Patent Reference 1).
There is a known voltage controlled oscillation circuit formed so as to have, for example, a configuration of FIG. 5. A voltage controlled oscillation circuit 400 of FIG. 5 includes a cascade connection of a voltage-to-current conversion circuit 410 and a current controlled oscillation circuit 420. The voltage-to-current conversion circuit 410 is a circuit for generating a current (i.e., an input voltage converted current) corresponding to an input voltage (i.e., an input voltage Vin). Moreover, the current controlled oscillation circuit 420 is a circuit of which an oscillation frequency is changed according to the input voltage converted current generated by the voltage-to-current conversion circuit 410.
The voltage-to-current conversion circuit 410 includes an N-channel MOS transistor 411, a P-channel MOS transistor 412 and a resistor 413.
The N-channel MOS transistor 411 has a gate connected to the input voltage Vin and a drain connected to a gate and a drain of the P-channel MOS transistor 412. A source of the N-channel MOS transistor 411 is grounded via the resistor 413. The P-channel MOS transistor 412 is a transistor constituting an input voltage converted current source and has a source connected to a power source VDD.
The current controlled oscillation circuit 420 includes delay cells provided in a plurality of stages. The number of stages of the delay cells may be an odd number larger than 2. In the following description, an example in which the current controlled oscillation circuit 420 includes delay cells 421 through 427 provided in seven stages will be shown. Although only two delay cells, i.e., delay cells 421 and 427 are illustrated in an example shown in FIG. 5, delay cells 422 through 426 are provided between the delay cells 421 and 427. That is, the delay cell 421 is a delay cell in the first stage and the delay cell 427 is a delay cell in the last stage. The delay cells all have the same configuration and, therefore, the delay cell 421, representing the delay cells, will be described.
As shown in FIG. 5, the delay cell 421 includes a P-channel MOS transistor 421a, a P-channel MOS transistor 421b, an N-channel MOS transistor 421c and a capacitor 421d. 
The P-channel MOS transistor 421a constitutes a current source. A source of the P-channel MOS transistor 421a is connected to a power source VDD, a drain thereof is connected to a source of the P-channel MOS transistor 421b. Moreover, a gate of the P-channel MOS transistor 421a is connected to a potential of a node of a gate and a drain of the P-channel MOS transistor 412 and a drain of the N-channel MOS transistor 411.
The P-channel MOS transistor 421b has a drain connected to a drain of the N-channel MOS transistor 421c and is grounded via the capacitor 421d. A source of the N-channel MOS transistor 421c is grounded.
Respective drains of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c which constitute a delay cell are connected to respective gates of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c of constituting a delay cell in the subsequent stage. Moreover, the drains (which will be referred to as output ends) of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c constituting a delay cell in the last stage are connected to respective gates of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c constituting a delay cell in the first stage.
The operation of the voltage controlled oscillation circuit 400 will be described.
First, the N-channel MOS transistor 411 is connected in a source follower connection. When the input voltage Vin is larger than Vth, a potential of a node (i.e., a node A) of the N-channel MOS transistor 411 and the resistor 413 is about (Vin−Vth). Vth is a threshold voltage of a transistor. Therefore, when the input voltage Vin is changed, the potential of the node A is changed. If a resistance value of the resistor 413 is R413, a current (i.e., an input voltage converted current value Io) flowing in the resistor 413 can be determined by:Io=(Vin−Vth)/R413.
An equal current to the above current flows in the N-channel MOS transistor 411 and the P-channel MOS transistor 412 constituting the input voltage converted current source. Accordingly, the input voltage Vin is shifted by Vth and thus a linear current to the input voltage Vin flows in the input voltage converted current source (i.e., the P-channel MOS transistor 412).
On the other hand, the potential of the gate and drain of the P-channel MOS transistor 412 and the drain of the N-channel MOS transistor 411, which determines a current of the input voltage converted current source (i.e., the P-channel MOS transistor 412), determines a current value of a current source (i.e., the P-channel MOS transistor 421a) in each delay cell in the current controlled oscillation circuit 420. Thus, respective current values of those current sources are equal to one another.
Subsequently, the operation of a delay cell will be described. When a voltage applied to the gates of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c in a delay cell is a Low level, the P-channel MOS transistor 421b passes a current and the N-channel MOS transistor 421c does not flow a current. In this case, a current value of a current which the P-channel MOS transistor 421b passes is determined by a current source (i.e., the P-channel MOS transistor 421a) in the delay cell and the current value is an input voltage converted current value Io. By this current, the capacitor 421d is charged with electric charges and the potential of a node of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c is increased.
Next, when the voltage applied to the gates of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c is increased from the Low level and exceeds the threshold voltage Vth of the N-channel MOS transistor 421c, the N-channel MOS transistor 421c passes a current. A current which the N-channel MOS transistor 421c passes is determined by a voltage applied to the gates of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c. Furthermore, when the voltage applied to the gates of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c is increased and an amount of the current which the P-channel MOS transistor 421b passes is larger than an amount of the current which the N-channel MOS transistor 421c passes, charges in the capacitor 421d are discharged and the potential of the node of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c drops. The delay cell repeats the above-described operation.
Next, the relationship between the input voltage converted current value Io and an oscillation frequency (i.e., an oscillation frequency fout) of an output signal Vout (i.e., a signal output from the drains of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c) will be described.
The relationship between the input voltage converted current value Io and the oscillation frequency fout of the output signal Vout is determined by the number of stages of delay cells. In this embodiment, the relationship between the input voltage converted current value Io and the oscillation frequency fout will be described using the case of delay cells in seven stages as an example.
FIG. 6 shows voltages applied to respective gates of P-channel MOS transistors 421b and N-channel MOS transistors 421c in the delay cells 421 through 427. When a voltage applied to the gates of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c in the delay cell 421 is the Low level, a voltage applied to each of the gates of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c in the delay cell 422 is increased. A current which the P-channel MOS transistor 421b in the delay cell 421 passes is determined by a current of the power source (i.e., the P-channel MOS transistor 421a) of the delay cell 421 and thus, as shown in FIG. 6, is increased in a constant slope.
When the voltage applied to the gates of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c in the delay cell 422 is increased and the current which the P-channel MOS transistor 421b passes is larger than the current which the N-channel MOS transistor 421c passes in the delay cell 422, the voltage applied to the gates of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c drops. At this time, the current which the N-channel MOS transistor 421c passes is determined by the voltage applied to the gates of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c in the delay cell 422, and thus rapidly drops to the Low level. By repeating the above-described operation by the delay cells, a signal with a predetermined oscillation cycle is output. The oscillation cycle is as follows.
If a voltage applied to the gates of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c when the voltage applied to the gates of the P-channel MOS transistor 421b and the N-channel MOS transistor 421c in a delay cell is increased and the current which the P-channel MOS transistor 421b passes and the current which the N-channel MOS transistor 421c passes are equal to each other is Vsw, a time which it takes to increase from the Low level to Vsw is Tsw and a capacitance value of the capacitor 421d is Co, the oscillation cycle can be expressed by:Tsw=Co×Vsw/Io. As shown in FIG. 6, in the case where delay cells are provided in seven stages, 1 cycle is 7×Tsw. In the same manner, in the case where delay cells are provided in n stages, since 1 cycle is n×Tsw, an oscillation frequency of the output signal Vout of the nth stage cell can be expressed by:
                    fout        =                  1          /                      (                          n              ×              Tsw                        )                                                  =                  Io          /                                    (                              n                ×                Co                ×                Vsw                            )                        .                              
Therefore, the relationship between the input voltage Vin and the oscillation frequency fout of the output voltage Vout is expressed by:fout=(Vin−Vth)/(n×Co×Vsw×R413).Therefore, the input voltage Vin is shifted by Vth and thus the oscillation frequency fout of the output signal Vout which is linear to the input voltage Vin is achieved.Patent Reference 1: Japanese Laid-Open Publication No. 5-145412